1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and particularly to a method of fabricating a multilevel interconnect.
2. Description of the Related Art
In integration circuit process for semiconductor devices, the interconnects are provided between two devices for allowing electrical connection between different devices or components. Aluminum is one conducting material that has been widely used to fabricating vias. The main reasons for the pervasiveness of aluminum are its low resistivity and its good adhesion to silicon oxides and silicon.
Referring to FIG. 1A, in the conventional process for manufacturing vias using aluminum, a wetting layer 18 formed of titanium is deposited in the via opening 16. An aluminum layer 20 is deposited by a sputtering process to fill the via opening 16. The wetting layers 18 and the aluminum layer 20 left in the via opening 16 form a via plug. The wetting layer 18 and the aluminum layer 20 on the dielectric layer 14 are patterned by photolithography process and an etch process, as shown in FIG. 1B.
In the above conventional process, the aluminum layer 20 formed by a sputtering process reacts with the titanium wetting layer 18 to form byproduct AlTi3 during the aluminum deposition step. Therefore, the step coverage of the aluminum layer 20 is affected and becomes poor. The via-filling process suffers from the poor step coverage, and voids 30 are formed in the via plug consequently. This affects the device reliability. In addition, the vias formed of aluminum further suffers an electromigration problem. More specifically, an annealing step is performed after the sputter deposition of aluminum, so that the aluminum is usually in poly-crystalline state. The aluminum atoms move along the grain boundary in an electric field, and the movement results in an open-circuit failure. This also affects device reliability.
The invention provides a method of fabricating interconnects. A semiconductor substrate having a dielectric layer is provided. The dielectric layer has at least a via opening, and the via opening expose a part of the semiconductor substrate. A titanium layer is formed along a surface profile of the via opening. The surface of the titanium layer is covered with an Alxe2x80x94Sixe2x80x94Cu alloy layer formed by a sputtering process at a substantially low temperature. The via openings are filled with an Alxe2x80x94Cu alloy layer formed by a sputtering process at a substantially high temperature, such that the Alxe2x80x94Cu alloy covers the surface of the Alxe2x80x94Sixe2x80x94Cu alloy layer.
In one preferred embodiment of the method of the present invention, the Alxe2x80x94Sixe2x80x94Cu alloy layer is formed at a temperature of about 0xc2x0 C. to about 200xc2x0 C. The composition of the Alxe2x80x94Sixe2x80x94Cu alloy layer has a silicon weight percentage of about 0.5% to about 1% and a copper weight percentage of about 0.4% to about 0.6%. The Alxe2x80x94Cu alloy layer is formed at a temperature from about 380xc2x0 C. to about 450xc2x0 C. The composition of the Alxe2x80x94Cu alloy layer has a copper weight percentage of about 0.4% to about 0.6%. The Alxe2x80x94Sixe2x80x94Cu alloy layer and the Alxe2x80x94Cu alloy layer comprise copper, so that the electromigration can be inhibited. The Alxe2x80x94Sixe2x80x94Cu alloy layer formed at a low temperature comprises silicon, so that the formation of the byproduct AlTi3 from the reaction of aluminum and titanium can be suppressed. Because the byproduct is suppressed from being formed, the Alxe2x80x94Sixe2x80x94Cu alloy layer thus inheres continuity which results in a good step coverage. In addition, the Alxe2x80x94Cu alloy layer is formed at a high temperature, which prevents the precipitation of silicon during the sputtering step of the Alxe2x80x94Cu alloy layer and avoids a silicon nodule after a metal etching step in the following process. The Alxe2x80x94Sixe2x80x94Cu alloy layer is between the Alxe2x80x94Cu alloy layer and the titanium layer, so that aluminum of the Alxe2x80x94Cu alloy layer does not react with titanium to produce AlTi3 byproducts. Thus, the step coverage of the Alxe2x80x94Cu alloy layer is not affected, and the filling problem can be suppressed. Therefore, the method of the present invention can be used to improve the step coverage and to avoid forming voids in the vias, so that the reliability of devices can be increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.